Detecting chip packaging defects is crucial for ensuring the reliability of high-end equipment in service. However, existing detection methods rarely deal with the problem of fast parallel switching of chip data types, and cannot effectively play a role in practical scenarios. In addition, in process quality feedback, decision-makers need to understand why the model classifies certain data as specific defect types. The deep model is often seen as "black boxes" that are difficult to explain the internal workings. To overcome the above drawbacks, an interpretable graph inference method inspired by time-frequency dynamic response mechanism is proposed. Firstly, a multi graph convolutional mapping network is built to extract topological level feature graph information from the source and target signals of the chip; Secondly, time-frequency convolution (TFC) kernels  with specific physical meanings is customized in the convolutional structure, so that the feature graph structure focuses on the components strongly related to defects; Then,  the time-frequency dynamic response mechanism is analyzed and  the number of activatable feature unit points is randomly selected during the training, enhancing the robustness of defect features; Finally, the interpretable conditional kernel Bures (CKB) inference criterion is embedded into the loss function of feature graph learning, improving the adaptability of defect features. Experiments were conducted on four typical defect detection tasks in different environments, and the results showed that the proposed method effectively improved the detection accuracy.

chip packaging defect detection, graph convolutional network, dynamic response, graph inferenc